The Real Reason Nvidia Is Building Custom CPU Cores
Nvidia didn't design the Vera CPU just to sell more server chips. It built it because standard server processors are becoming the biggest bottleneck in AI infrastructure.
When you run agentic AI—where models write code, call external APIs, query databases, and execute multi-step reasoning loops—the GPU isn't doing all the work. It spends significant time waiting on a host processor to fetch data, handle control flow, and run untrusted code in sandboxed environments.
For years, Nvidia relied on third-party Arm designs like Grace. But with its next-generation Vera chip, Team Green went all-in on a ground-up custom architecture called Olympus. This isn't just another incremental enterprise processor. It's a direct shot across the bows of x86 giants AMD and Intel, tailored for a market transition that traditional chips weren't engineered to handle.
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| Nvidia Vera CPU |
| 88 Custom Olympus Armv9.2 Cores |
+-----------------------+-------------------------+
|
| 3.4 TB/s
v
+-------------------------------------------------+
| Scalable Coherency Fabric (164 MB L3 Cache) |
+-----------------------+-------------------------+
|
+-----------------------+-------------------------+
| |
v v
+-----------------------------+ +-----------------------------+
| 1.2 TB/s SOCAMM2 LPDDR5X | | 1.8 TB/s NVLink-C2C |
| (Up to 1.5 TB Ram) | | Direct to Rubin GPUs |
+-----------------------------+ +-----------------------------+
Under the Hood of the Olympus Architecture
Vera sports 88 custom Olympus cores supporting 176 hardware threads. Rather than competing purely on core count, Nvidia focused on raw single-threaded execution speed, instruction pipeline width, and memory delivery.
The Olympus core features a wide front end built around a neural branch predictor and a 10-wide instruction decoder capable of feeding execution units without stalling. That matters because AI agent software is messy. Unlike predictable graphics math, agent code is full of conditional jumps, complex pointer chains, and abrupt logic changes.
To keep those 88 cores fed, Nvidia engineered a series of platform features:
- Spatial Multithreading (SMT): Traditional simultaneous multithreading often leads to context thrashing, where two threads compete for core cache and stall each other. Nvidia's Spatial Multithreading lets the chip dynamically partition execution resources, allowing one high-priority thread to run at full speed while a secondary thread manages background OS tasks without causing interference.
- Monolithic Die with Uniform Access: AMD and Intel construct high-core-count processors using multiple small chiplets. While cheaper to produce, chiplets introduce non-uniform memory access (NUMA) delays. Vera uses a single large, monolithic compute die. Every single core sits at an identical latency distance from the 164 MB shared L3 cache.
- Second-Gen Scalable Coherency Fabric: The on-die fabric pushes up to 3.4 TB/s of bi-sectional bandwidth, letting all cores query shared memory space without hitting latency walls.
- SOCAMM2 LPDDR5X Memory: Instead of traditional registered DDR5 server DIMMs, Vera integrates SOCAMM2 low-power memory modules. This yields up to 1.2 TB/s of aggregate memory bandwidth (14 GB/s per core) while drawing a fraction of the power required by conventional server memory channels.
How Vera Compares to AMD Turin and Intel Granite Rapids
Nvidia isn't competing for general-purpose cloud web hosting or basic enterprise database hosting. It's targeting the high-margin tier of data center compute.
The benchmark numbers illustrate a clear strategy. In early SPEC CPU testing, Vera nudged past AMD's top-end EPYC 9755 Turin processor in total throughput—despite running significantly fewer total threads. When it comes to single-threaded responsiveness and instruction-per-clock (IPC) efficiency in agent runtime sandboxes, Nvidia claims up to a 50% speed advantage over competing x86 platforms.
| Feature / Metric | Nvidia Vera | AMD EPYC (Turin) | Intel Xeon 6 (Granite Rapids) |
|---|---|---|---|
| Primary Architecture | Custom Armv9.2 (Olympus) | x86 (Zen 5 / Zen 5c) | x86 (P-Cores / E-Cores) |
| Max Cores / Threads | 88 Cores / 176 Threads | Up to 192 Cores / 384 Threads | Up to 128 Cores / 256 Threads |
| Silicon Layout | Monolithic compute die | Multi-chiplet design | Multi-tile chiplet design |
| Interconnect Speed | 1.8 TB/s NVLink-C2C | PCIe Gen 5 / CXL | PCIe Gen 5 / CXL |
| Memory Technology | SOCAMM2 LPDDR5X (1.2 TB/s) | DDR5 / MRDIMM | DDR5 / MRDIMM |
| Target Load Focus | Agentic AI, sandboxing, data pipelines | Cloud density, massive throughput | Legacy enterprise, general compute |
AMD retains an advantage in pure multi-threaded parallel brute force, particularly with high-density chips like its Zen 6 "Venice" designs coming down the pipe. But raw core count misses the point of Vera. Nvidia designed this chip around the host-to-accelerator link.
The killer spec isn't the core count. It's the 1.8 TB/s NVLink-C2C interface that connects Vera directly to Rubin GPUs. That link provides unified memory coherence at twice the bandwidth of the previous Grace generation and orders of magnitude faster than standard PCIe slots. The CPU and GPU read from the exact same memory space with almost zero handoff overhead.
Why the Market Split Is Widening
We're witnessing a fundamental split in server architecture.
AMD and Intel are defending the legacy x86 footprint. Millions of enterprise software stacks, virtual machines, and cloud services run on x86, and those systems aren't disappearing anytime soon. Both chipmakers continue to pack more cores into sockets to maximize virtualization density per rack.
Nvidia is pursuing an entirely different playbook. It doesn't care about backward compatibility with 15-year-old enterprise software. It wants to own the "AI Factory"—a dedicated data center setup where racks of GPUs run full throttle 24/7.
By packaging 256 Vera CPUs into liquid-cooled rack configurations capable of handling over 22,500 concurrent execution sandboxes, Nvidia offers a turnkey solution for AI developers. Companies building massive agentic platforms like OpenAI and Anthropic are already taking early deliveries. They don't want to engineer host bottlenecks out of their software; they want hardware that eliminates the bottleneck by design.
How to Plan Your Infrastructure Strategy
If you're evaluating data center hardware investments over the next 24 to 36 months, stop viewing CPUs through the lens of generic core counts. Match your processor selection directly to your operational bottlenecks.
- Audit your software execution profiles: Check where your application logic actually spends its cycles. If your AI pipelines spend most of their time doing standard batch inference or straight vector math on GPUs, traditional x86 host nodes running EPYC or Xeon remain cost-effective.
- Identify agentic sandboxing bottlenecks: If your stack heavily relies on tool-calling, runtime code execution, complex ETL, or real-time data orchestration before feeding a model, calculate the latency cost of your CPU-to-GPU link. High thread latency in those steps directly starves your expensive GPUs.
- Assess thermal and power constraints: Vera relies on high-density liquid cooling setups (like the MGX NVL72 architecture). If your data center facilities aren't equipped for direct-to-chip liquid cooling, adopting full Vera racks will require facility upgrades.
- Evaluate lock-in versus performance gains: Choosing Nvidia's full Vera-Rubin stack locks your system orchestration deeply into Nvidia's hardware and software ecosystem. Balance the tight integration benefits against the flexibility of open x86 standard servers paired via standard PCIe buses.
